1. Field of the Invention
The present invention relates to a substrate processing apparatus and a substrate processing method, and particularly relates to a technology for preventing surface abnormalities and corrosion in metal wiring from being formed using chemical mechanical polishing.
2. Description of the Related Art
Metal wiring is widely used as wiring to compose a semiconductor integrated circuit device (hereafter, referred to as a semiconductor device). Conventionally, the metal wiring has been formed by means of a metal film deposited onto a silicon substrate (wafer) with the application of lithography technology and etching technology. This type of metal film includes aluminum (Al) alloy film and tungsten (W) film by sputtering technology.
Associated with recent high-integration of semiconductor devices, in the metal wiring formed using the above technique, increased wiring resistance associated with a reduction of wiring width becomes remarkable. Particularly in sophisticated logic LSIs (large scale integrated circuits), the increase of the wiring resistance is a significant factor interfering with performance. In semiconductor devices with 0.13 μm or less of minimum wiring line width, metal wiring using copper (Cu) the electric resistance of which is approximately one-half of that of Al alloy, and whose electro-migration resistance is approximately 10 times higher than that of the Al alloy is noticed, and actually used.
Because the vapor pressure of a Cu halogenated compound is low, it is difficult for Cu to process by dry etching, which has been historically used. Consequently, for the formation of Cu wiring, a process to polish back (in a so-called dual damascene process) using a chemical mechanical polishing (CMP) method is used. In this process, after a Cu film is deposited onto an insulating film where a via-hole and a trench is pre-formed, an unnecessary Cu film outside the via-hole and the trench is removed by CMP processing and Cu fills the via-hole and the trench. Furthermore, an adhesion layer, such as tantalum nitride (TaN) film, for preventing the Cu film from peeling off, and a barrier metal, such as a tantalum (Ta) film, for preventing diffusion of Cu into the insulating film, are sequentially deposited as a lower layer of the Cu film.
In the mass-production process for the semiconductor devices equipped with copper wiring, in order to improve production capability, use is made of a CMP apparatus equipped with multiple platens. For example, in a CMP apparatus equipped with two polishing platens, a Cu film is polished up to a boundary surface with a barrier metal or a boundary surface the adhesion layer by a first polishing platen. In this case, any remaining barrier metal and an adhesion layer are polished by a second polishing platen. Further, in a CMP apparatus equipped with three polishing platens, a Cu film is polished halfway by the first polishing platen, and the Cu film is polished up to a boundary surface with a barrier metal surface or the boundary surface with an adhesion layer by the second polishing platen. In this case, any remaining barrier metal and adhesion layer are polished by the third polishing platen. As described, in a CMP apparatus equipped with multiple polishing platens, a method where different stages of polishing are conducted in parallel and consecutively by the polishing platens is often adopted. Furthermore, in this CMP apparatus, the polishing slurry used for each polishing platen is different.
In each polishing platen, after polishing is complete, ultrapure water is supplied to the wafer surface. After the polishing slurry on the wafer surface is removed to some extent by the ultrapure water, the wafer is conveyed to the next polishing platen and polishing is conducted in the next stage. Further, after CMP processing where the final stage polishing has been completed, the wafer is cleaned by a cleaning section, which is integrally constructed with the CMP apparatus, or a cleaning apparatus, which is a separate body from the CMP apparatus.
In cleaning after CMP processing, in order to assuredly remove particles remaining on the wafer surface, it is essential to convey a polished but not-dried wafer to the cleaning section (cleaning apparatus) for cleaning. Therefore, a mechanism is arranged where the ultrapure water is sprayed onto a wafer from a nozzle in a route where a wafer is conveyed.
In the copper wiring formation process described above, it is necessary to prevent corrosion of the copper wiring during CMP processing or after the completion of CMP processing. As the corrosion of the copper wiring, reference can be made to corrosion caused by an oxidant contained in a polishing slurry, and electrochemical corrosion due to a cell action in a closed circuit composed of a metal pattern of a lower layer, PN junction and a polishing slurry. In order to prevent this corrosion, a rust-proofing treatment is applied to the copper wiring by coating a corrosion inhibitor onto the wafer surface. The rust-proofing treatment may be conducted immediately after the polishing slurry on the wafer surface is removed to some extent by the ultrapure water after polishing is complete. However, in the mass-production process of the semiconductor devices, due to the restriction of throughput, polishing slurry where the corrosion inhibitor is added, such as BTA (Benzo-Tri-Azole: C6H5N3), is used, and rust-proofing treatment is applied at the same time as polishing. Because of the rust-proofing treatment, if the CMP apparatus is normally shielded from light, the corrosion of the copper wiring can be prevented to some extent, which is problematic for practical use.
In the meantime, when the copper wiring is exposed to light while it is wet, it is known that photocorrosion occurs on the copper wiring. To prevent this, various technologies to prevent the photocorrosion of the copper wiring are proposed. For example, Japanese Unexamined Patent Application Publication 2002-93760 proposes a method where when a polished wafer is conveyed to a cleaning apparatus, a solution containing a corrosion inhibitor, such as BTA, is supplied to the wafer that is in reserve for conveyance. With this technique, the surface of the completely polished wafer is retained while it is wet with the solution containing a corrosion inhibitor. Consequently, it is said that even when the wafer is exposed to light, corrosion of the copper wiring can be prevented.
Further, Japanese Unexamined Patent Application Publication 2005-109094 proposes another technique where multiple illuminometers are arranged within a processing section, such as a polishing section or a cleaning/drying section where a wetting processing is applied while the copper wiring is exposed to the wafer surface, and the luminance is monitored in real time. In the technique, if any of the illuminometers detects brightness that exceeds, for example, 50 1x, the wetting processing for the processing section exceeding 50 1x is stopped. Consequently, the wetting processing will never be continuously applied in the light exposure state, preventing the mass generation of corrosion defects.